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HS-26CLV32RH
Data Sheet May 28, 2009 FN4907.2
Radiation Hardened 3.3V Quad Differential Line Receiver
The Intersil HS-26CLV32RH is a radiation hardened 3.3V quad differential line receiver designed for digital data transmission over balanced lines, in low voltage, RS-422 protocol applications. Radiation hardened CMOS processing assures low power consumption, high speed, and reliable operation in the most severe radiation environments. The HS-26CLV32RH has an input sensitivity of 200mV (Typ) over a common mode input voltage range of -4V to +7V. The receivers are also equipped with input fail safe circuitry, which causes the outputs to go to a logic "1" when the inputs are open. The device has unique inputs that remain high impedance when the receiver is disabled or powered-down, maintaining signal integrity in multi-receiver applications. Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed here must be used when ordering. Detailed Electrical Specifications for these devices are contained in SMD 5962-95689. A "hot-link" is provided on our homepage for downloading. www.intersil.com/military/
Features
* Electrically Screened to SMD # 5962-95689 * QML Qualified per MIL-PRF-38535 Requirements * 1.2 Micron Radiation Hardened CMOS - Total Dose. . . . . . . . . . . . . . . . . . . . . 300 krad(Si)(Max) - Single Event Upset LET . . . . . . . . . . . 100MeV/mg/cm2) - Single Event Latch-up Immune * Low Stand-by Current . . . . . . . . . . . . . . . . . . .13mA(Max) * Operating Supply Range . . . . . . . . . . . . . . . . 3.0V to 3.6V * Enable Input Levels . . .VIH > (0.7)(VDD); VIL < (0.3)(VDD) * CMOS Output Levels . . . . . . . . VOH > 2.55V; VOL < 0.4V * Input Fail Safe Circuitry * High Impedance Inputs when Disabled or Powered-down * Full -55C to +125C Military Temperature Range * Pb-Free (RoHS Compliant)
Applications
* Line Receiver for MIL-STD-1553 Serial Data Bus
Logic Diagram
ENABLE ENABLE DIN DIN CIN CIN BIN BIN AIN AIN
+
-
+
-
+
-
+
-
DOUT
COUT
BOUT
AOUT
Ordering Information
ORDERING NUMBER (Note) 5962F9568902QEC 5962F9568902QXC 5962F9568902VEC 5962F9568902VXC HS1-26CLV32RH/PROTO HS9-26CLV32RH/PROTO INTERNAL MKT. NO. HS1-26CLV32RH-8 HS9-26CLV32RH-8 HS1-26CLV32RH-Q HS9-26CLV32RH-Q HS1-26CLV32RH/PROTO HS9-26CLV32RH/PROTO PART MARKING Q 5962F95 68902QEC Q 5962F95 68902QXC Q 5962F95 68902VEC Q 5962F95 68902VXC HS1- 26CLV32RH /PROTO HS9- 26CLV32RH /PROTO TEMP. RANGE (C) -55 to +125 -55 to +125 -55 to +125 -55 to +125 -55 to +125 -55 to +125 PACKAGE (Pb-Free) 16 Ld SBDIP PKG. DWG. # D16.3
16 Ld FLATPACK K16.A 16 Ld SBDIP D16.3
16 Ld FLATPACK K16.A 16 Ld SBDIP D16.3
16 Ld FLATPACK K16.A
NOTE: These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2000, 2008, 2009.All Rights Reserved All other trademarks mentioned are the property of their respective owners.
HS-26CLV32RH Pinouts
HS1-26CLV32RH (16 LD SBDIP) MIL-STD-1835: CDIP2-T16 TOP VIEW
AIN 1 AIN 2 AOUT 3 ENABLE 4 COUT 5 CIN 6 CIN 7 GND 8 16 VDD 15 BIN 14 BIN 13 BOUT 12 ENABLE 11 DOUT 10 DIN 9 DIN AIN AIN AOUT ENABLE COUT CIN CIN GND
HS9-26CLV32RH (16 LD FLATPACK) MIL-STD-1835: CDFP4-F16 TOP VIEW
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD BIN BIN BOUT ENABLE DOUT DIN DIN
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 2
FN4907.2 May 28, 2009
HS-26CLV32RH Die Characteristics
DIE DIMENSIONS: 84 mils x 130 mils x 21 mils (2140m x 3290m) INTERFACE MATERIALS: Glassivation: Type: PSG (Phosphorus Silicon Glass) Thickness: 8kA 1kA Substrate: AVLSI1RA, Silicon backside, VDD backside potential Metallization: Bottom: Mo/Tiw Thickness: 5800A 1kA Top: Al/Si/Cu Thickness: 10kA 1kA Worst Case Current Density: <2.0 x 105A/cm2 Bond Pad Size: 110m x 100m
Metallization Mask Layout
HS-26CLV32RH TABLE 1. HS26CLV32RH PAD COORDINATES
AIN (1) VDD (16) BIN (15)
RELATIVE TO PIN 1 PIN NUMBER 1 2 PAD NAME AIN AIN AOUT ENABLE COUT CIN CIN GND DIN DIN DOUT ENABLE BOUT BIN BIN VDD X Y COORDINATES COORDINATES 0 -337.1 -337.1 -337.1 -337.1 -337.1 0 418.4 776.4 1113.5 1113.5 1113.5 1113.5 1113.5 776.4 420.2 0 -362 -912.5 -1319.3 -1774.4 -2233.7 -2595.7 -2596.7 -2595.7 -2233.7 -1774.4 -1319.3 -898.4 -362 0 1
AIN (2)
(14) BIN
3 4 5 6
AOUT (3)
(13) BOUT
7 8 9
ENAB (4)
(12) ENAB
10 11 12
COUT (5)
(11) DOUT
13 14 15 16
CIN (6)
(10) DIN
NOTE: Dimensions in microns
(7) CIN
(8) GND
(9) DIN
3
FN4907.2 May 28, 2009

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